The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can secure margins of setup/hold times of an address.
A semiconductor memory device is provided with an address buffering unit for buffering external addresses. The address buffering unit latches the buffered addresses using an internal clock as a strobe signal.
FIG. 1 is a block diagram of a conventional address buffering unit.
The address buffering unit includes a buffering unit 110 and a latching unit 120. The buffering unit 110 receives addresses from an external chipset to buffer the addresses to an internal CMOS level of a semiconductor memory device. The latching unit 120 synchronizes the buffered addresses ADD_OUT received from the buffering unit 110 with an internal clock CLK_ADD, thereby outputting an internal addresses AN.
The addresses are input in synchronization with a rising edge of an external clock with margins of setup/hold times, and then latched in synchronization with a rising edge of the internal clock. This is referred to as a single data rate (SDR) type. However, in the Graphics Double Data Rate, version 5 (GDDR5) Dynamic Random Access Memory (DRAM), the addresses are input in synchronization with rising/falling edges of the external clock with margins of setup/hold times, and then latched in synchronization with both rising/falling edges of the internal clock. This is referred to as a double data rate (DDR) type.
This means that the addresses are transferred at the same speed as data at a data bit rate of GDDR3/GDDR4 DRAM. That is, when tCK=1 GHz, the addresses are transferred at a speed of 1 Gbps and the data is input/output in synchronization with rising/falling edges of a clock to be transferred at a speed of 2 Gbps in GDDR3/GDDR4 DRAM. However, in a GDDR5 DRAM, the addresses are also input in synchronization with both the rising/falling edges of the clock to be transferred at a speed of 2 Gbps. This may decrease a reliability of the address input.
In the conventional GDDR DRAM, a DQS signal, which is a data strobe signal, is input in synchronization with a data DQ at every one byte (every eight DQ's) to secure a bit rate of 2 Gbps of the data DQ. The DQS signal serves to latch the data DQ, and the data DQ and the DQS signal are source-synchronized signals transferred in the same path from a chipset to the memory device. Therefore, reliability of inputting the data DQ can be secured.
In the GDDR5 DRAM, the addresses are input in the DDR type manner and thus at the same speed as the data DQ. However, the addresses are input in synchronization with the external clock instead of a source-synchronized signal such as the DQS signal. Therefore, it is difficult to secure margins of the setup/hold times for latching the addresses.